| Name | Version | Summary | date |
| mio-cli |
1.3.8 |
The Moore.io Command Line Interface (CLI) Client is a toolchain for front-end engineering of FPGA/ASIC projects. |
2024-05-17 12:13:59 |
| zhixin |
6.1.16a3 |
Your Gateway to Embedded Software Development Excellence. Unlock the true potential of embedded software development with ZhiXin's collaborative ecosystem, embracing declarative principles, test-driven methodologies, and modern toolchains for unrivaled success. |
2024-05-17 03:01:58 |
| ivpm |
1.1.2.9116518260 |
IVPM (IP and Verification Package Manager) is a project-internal package manager. |
2024-05-16 17:20:39 |
| tsfpga |
12.3.3 |
A flexible and scalable development platform for modern FPGA projects |
2024-05-14 07:47:37 |
| pyhdl-if |
0.0.1.9053152306 |
Python interface for HDL programming interfaces |
2024-05-12 17:42:56 |
| platformio |
6.1.15 |
Your Gateway to Embedded Software Development Excellence. Unlock the true potential of embedded software development with PlatformIO's collaborative ecosystem, embracing declarative principles, test-driven methodologies, and modern toolchains for unrivaled success. |
2024-04-25 08:52:24 |
| pyslang |
6.0 |
Python bindings for slang, a library for compiling SystemVerilog |
2024-04-22 03:09:17 |
| pyhdl-call-if |
0.0.1.8682446142 |
Python interface for HDL programming interfaces |
2024-04-15 02:48:41 |
| pyhdl-tlm-if |
0.0.1 |
Python interface for HDL programming interfaces |
2024-04-13 19:18:52 |
| pyhdl-pi-if |
0.0.1.8675558542 |
Python interface for HDL programming interfaces |
2024-04-13 18:44:50 |
| super-ide |
1.4.8 |
A professional Cross-platform IDE. Cross-platform IDE and Unified Debugger. Static Code Analyzer and Remote Unit Testing. Multi-platform and Multi-architecture Build System. Firmware File Explorer and Memory Inspection. IoT, Arduino, CMSIS, ESP-IDF, FreeRTOS, libOpenCM3, mbedOS, Pulp OS, SPL, STM32Cube, Zephyr RTOS, ARM, AVR, Espressif (ESP8266/ESP32), FPGA, MCS-51 (8051), MSP430, Nordic (nRF51/nRF52), NXP i.MX RT, PIC32, RISC-V, STMicroelectronics (STM8/STM32), Teensy |
2024-04-05 05:04:27 |
| pyvsc-dataclasses |
0.0.1.8548344824 |
Front-end for capturing Verification Stimulus and Coverage constructs using dataclasses |
2024-04-04 02:20:33 |
| peakrdl-regblock |
0.22.0 |
Compile SystemRDL into a SystemVerilog control/status register (CSR) block |
2024-04-01 05:27:07 |
| vsc-solvers |
0.0.1.8469955330 |
Core Verification Stimulus and Coverage library |
2024-03-28 15:51:20 |
| verilog-pad-analyzer |
0.0.6 |
VerilogPADAnalyzer is a Python application designed to analyze and report the |
2024-03-26 11:17:12 |
| zuspec-cli |
0.0.1.8428737035 |
Co-specification of hardware, software, design, and test behavior |
2024-03-26 00:13:38 |
| pyapi-compat-if |
0.0.1.8428028712 |
Core Verification Stimulus and Coverage library |
2024-03-25 22:51:34 |
| zuspec-arl-eval |
0.0.1.8427873686 |
Core ARL data model library |
2024-03-25 22:37:52 |
| zuspec-be-py |
0.0.1.8427800336 |
Co-specification of hardware, software, design, and test behavior |
2024-03-25 22:25:10 |
| zuspec-py |
0.0.3.8422382174 |
Co-specification of hardware, software, design, and test behavior |
2024-03-25 15:12:06 |